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24AA64/24LC64
4.0
4.1
WRITE OPERATIONS
Byte Write
Note: Page write operations are limited to writ-
ing bytes within a single physical page,
regardless of the number of bytes actu-
Following the START condition from the master, the
control code (four bits), the chip select (three bits), and
the R/W bit (which is a logic low) are clocked onto the
bus by the master transmitter. This indicates to the
addressed slave receiver that the address high byte will
follow after it has generated an Acknowledge bit during
the ninth clock cycle. Therefore, the next byte transmit-
ted by the master is the high-order byte of the word
address and will be written into the address pointer of
the 24XX64. The next byte is the Least Significant
Address Byte. After receiving another Acknowledge
signal from the 24XX64 the master device will transmit
the data word to be written into the addressed memory
location. The 24XX64 acknowledges again and the
master generates a STOP condition. This initiates the
ally being written. Physical page bound-
aries start at addresses that are integer
multiples of the page buffer size (or
‘page size’) and end at addresses that
are integer multiples of [page size - 1]. If
a page write command attempts to write
across a physical page boundary, the
result is that the data wraps around to
the beginning of the current page (over-
writing data previously stored there),
instead of being written to the next page
as might be expected. It is therefore
necessary for the application software to
prevent page write operations that
would attempt to cross a page boundary.
internal write cycle, and during this time the 24XX64
will not generate Acknowledge signals (Figure 4-1). If
4.3
Write Protection
an attempt is made to write to the array with the WP pin
held high, the device will acknowledge the command
but no write cycle will occur, no data will be written and
the device will immediately accept a new command.
After a byte write command, the internal address
counter will point to the address location following the
one that was just written.
The WP pin allows the user to write protect the entire
array (0000-1FFF) when the pin is tied to V CC . If tied to
V SS or left floating, the write protection is disabled. The
WP pin is sampled at the STOP bit for every write com-
mand (Figure 3-1) Toggling the WP pin after the STOP
bit will have no effect on the execution of the write
cycle.
4.2
Page Write
The write control byte, word address and the first data
byte are transmitted to the 24XX64 in the same way as
in a byte write. But instead of generating a STOP con-
dition, the master transmits up to 31 additional bytes
which are temporarily stored in the on-chip page buffer
and will be written into memory after the master has
transmitted a STOP condition. After receipt of each
word, the five lower address pointer bits are internally
incremented by one. If the master should transmit more
than 32 bytes prior to generating the STOP condition,
the address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the STOP condition is received, an
internal write cycle will begin (Figure 4-2). If an attempt
is made to write to the array with the WP pin held high,
the device will acknowledge the command but no write
cycle will occur, no data will be written and the device
will immediately accept a new command.
? 2002 Microchip Technology Inc.
DS21189F-page 7
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